1. Field of the Invention
The present invention relates to a novel method and system for optimizing integrated circuit layouts, generally, and particularly, a system and method for modeling performance of a semiconductor device structure for achieving modified ground rules for lithographic feature distances that optimize semiconductor device performance.
2. Description of the Prior Art
Lithographic constraints are important factors in determining the efficiency of a circuit layout. In essence, lithographic constraints are conventionally determined by the generally limited capability of a lithographic process to successfully print line features at specified positions within tolerances. A lithographic process involves using a lithographic exposure tool to illuminate a lithographic mask from a range of directions, and focusing a projected image of the mask onto a photosensitive film that coats a partially fabricated integrated circuit on a wafer, such as a silicon wafer. Lithographic process window represents the range of delivered light energy (dose) and image plane defocus within which the projected image adequately represents the desired circuit shapes. After the image is formed, the photosensitive film is developed, and the printed pattern is transferred into a functional process layer in the circuit. The final circuit then consists of many such patterned levels stacked atop one another.
FIG. 1A shows an example portion of a semiconductor device structure 10, e.g., including a FET device such as a pFET, suitable for characterizing a lithographic process impact on device performance. This device structure 10 includes an active device area (alternately referred to as “RX”) 15 having an L shape, where the narrower width dimension “W” is formed on a semiconductor substrate and comprises, for example, a polysilicon gate or gate stack 25 (not shown) that separates source and drain regions each represented by contacts 29 and 29′. As shown in FIG. 1A, the active device area is characterized as having a “flare” region 12. This “flared” region, in the example depiction of FIG. 1A, is caused by the need for joining two devices that have different widths W and W2 and a common source or drain 29. The second device comprises a second gate 25′ with device width W2 with contacts 29 and 29″ to the source and drain regions. The contact 29 is common to both devices with gates 25 and 25′. Upon lithographic processing of the active area 15, the corner 30 rounds and the device width W of gate 25 is changed. This is considered a width expansion and the impact of the process on device characteristics needs to be assessed.
In an alternate example, as depicted in FIG. 1B, a semiconductor device structure 10′ includes two flared regions 12 and 12′ are exemplified. The flared regions 12 and 12′ have two corners 30 and 30′ in FIG. 1B which round upon lithographic processing and change the device width W.
In each embodiment depicted in FIGS. 1A, 1B, the conductive wire or line layer 25 and 25′ (alternately referred to as “PC”) comprising a conductive material, for example, polysilicon, is electrically coupled to the gate (not shown) and extends at either side of the active device area 15. Further as shown in FIGS. 1A and 1B are formed source and drain contact metallurgy such as 29, 29′, and 29″ formed at either side of the conductive line layer 25 for providing electrical contact to the active devices as known in the art.
Moreover, as the width flaring resulting from the lithographic processes may impact the “true” device width, the Ion current data (transistor data) for that device will accordingly vary. That is, for the structures shown in the example flaring of circuitry 10 in FIGS. 1A, 1B, significant current variation will be evident in dependence upon the RX width. Therefore, it is the case that any compact modeling used needs to account for the device performance effect in the model. That is, in the migration to 45 nm CMOS fabrication processes, the compact model for devices needs device performance effect in model.
Acceptable tolerances for the printed shapes must yield successful circuit performance, and must also be readily maintained under typical process variations. However, lithographic capability for printing a given feature edge is dependent on other features in the same local region of the circuit layout, as is circuit functionality. Consequently, lithographic constraints should ideally be very dynamic, and potentially incorporate and take advantage of the particular configurational details of large numbers of different local circuit cases.
Generally, however, due to general and practical design reasons, lithographic constraints are usually provided in a highly simplified form, known in the technology as design rules or ground rules, with these rules determining a lithographic capability, in effect, an achievable lithographic process window, which is at least acceptable in the technology, and these rules are normally employed for the entire circuit layout.
Thus, in the migration to 45 nm CMOS fabrication processes, e.g., of the device structures shown in FIGS. 1A, 1B, there is a need for a ground rules at a point where device performance is negatively affected.
Moreover, it would be highly desirable to provide a method and system for more accurately modeling semiconductor device performance by taking into account the impact of lithographic corner rounding effects, such as those effects that impact the RX area of a semiconductor device.